1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device of a daisy chain structure having an independent refresh apparatus which can perform a refresh operation in each of a number of DRAMs by itself by adding the independent refresh apparatus to the DRAMs formed in a ring shape.
2. Description of the Prior Art
Generally, in an DRAM having a ring type structure such as R-DRAM with a RAMBUS structure or SYNCLINK structure as a constitution of a DRAM, when a refresh operation is performed in a cell (specifically, in a power-down mode), a number of DRAMs perform in sequence the refresh operation by means of refresh operation control signals which are provided from a controller.
Wherein, semiconductor device having a daisy chain or the ring type includes a controller to control a number of DRAMs, the controller are continuously connected with a number of DRAMs in a serial fashion, and each of DRAMs is sequentially controlled by the controller.
The daisy chain construction will be explained with reference to FIG. 1. FIG. 1 is a block diagram of a semiconductor device of a daisy chain type indicating a connection between the plurality of DRAMs (i.e., semiconductor memory device) and the system, and illustrating that the DRAMs (DRAM0-DRAMn) 10 having input/output terminals Si/So are connected in a serial fashion to one another and that controller 20 is also connected with each DRAM to commonly control the plurality of DRAMs.
At this event, the controller 20 outputs refresh operation signals SR0 to one of DRAMs which is connected most adjacently thereto and outputs enable signals to control an operation of a decoder section in each DRAM section.
FIG. 2 shows a detailed block diagram of one of the DRAMs which includes a buffer 11 for storing the signals inputted through the input terminals Si, a delay section 12 for delaying the signals outputted from the buffer 11 for a predetermined time and then outputting them, a decoder section 13 for decoding the signals outputted from the buffer 11, to check whether a DRAM identification number ID which is presently inputted is equal to an other DRAM identification number ID which is set in an initial step, and for outputting refresh control signals C1 to refresh the cell, and a RAM circuit section 14 for refreshing the cell by applying the input control signals C1 outputted from the decoding section 13.
In the semiconductor device formed in the above manner, a refresh operation through the DRAM being most adjacent to the controller are performed as below.
First, if a refresh signal SR0 is inputted in the controller 20, the refresh signal is stored in the buffer 11 and an output of the buffer 11 is inputted to both the decoding section 13 and the delay section 12.
The decoding section 13 decodes the inputted signals and checks whether the signals inputted from the controller 20 is identical to the identification number of DRAMs in operation, thereby controlling a preformation of the refresh operation in the RAM circuit section 14. Subsequently, if the refresh operation of the RAM circuit section 14 is performed, the control signals C1 are inputted to the delay section 12 so that the refresh signals which is on latching are outputted to the next DRAM.
Subsequently, a second DRAM receiving the refresh signals performs the same operation in a similar manner,, and such a same operation is operated with respect to rest DRAMs being connected in a chain.
However, in a refresh method according to the conventional daisy chain structure as above, DRAMs are refreshed in sequence through the refresh signals outputted from the single controller 20, and the controller 20 has to generate and input the signals used in the refresh operation.
Accordingly, there is a problem that since the DRAM itself does not perform either a refresh operation or an operation of signal generation, it causes a restriction in applying such a kind of DRAM circuit.
An object of the present invention to solve the problem involved in the conventional technology is to provide a semiconductor device to independently perform a refresh operation with separating status from a controller by using a power-down register value and generating refresh signals in DRAMs themselves.
Semiconductor device having a plularity of memory devices of a daisy chain, each of the memory devices comprising: clock generation section for generating a clock signal used for a refresh operation in accordance with a logic level of a power-down register which is set in a power-down mode, address count means for generating an internal row address by counting the clock signal applied from the clock generation section, and cell array block being refreshed by a refresh operation in response to the internal address outputted from the address count means.
Further, a semiconductor device of a daisy chain structure in accordance with the present invention to perform the above operation, which includes a controller and a number of semiconductor memory devices connected to the controller, is characterized by comprising a number of semiconductor memory devices which are connected to one another to independently perform a refresh operation processed in the memory devices by means of an internal address which generates by itself so that the semiconductor memory devices can perform an internal refresh operation by receiving a power-down register value provided from the controller.